The invention relates to a memory having redundant storage space, which memory comprises address inputs via which address bits can be supplied, a plurality of predecoders, each of which outputs predecoded address bits, after the supply of a part of said address bits, and a main address decoder which is connected to the precoders and which comprises logic gate circuits, each of which comprises a number of inputs which corresponds at least to the number of precoders, a selection bit for controlling a memory column being derived in said logic gate circuits from the supplied predecoded address bits, the main address decoder comprising for each memory column a fuse element for uncoupling the relevant memory column in the case of a defect therein, which memory also comprises a redundancy address decoder which is fed by all outputs of the precoders via a corresponding number of fuse elements associated with the redundancy address decoders and which supplies, in the case of a defect in a memory column and after the uncoupling of the relevant fuse elements, a selection bit for a substitute redundant memory column.
Notably in large memories one or more redundant memory rows and/or columns are added in order to enable replacement of a relevant row or column by a redundant memory row or column in the case of a defect in the memory, so that the memory can be considered to have been repaired. Repair is realized, for example by the opening of fuse elements provided in the memory for this purpose, that is to say so that, when a defective memory row or column is addressed, the memory address presented is replaced by the address of a redundant memory row or column. The logic customarily used for this purpose consists of a circuit in which every memory address presented is compared with that of the defective row or column. When these two addresses correspond, the redundant row or column in the memory is activated.
The addition of redundant memory rows and/or column may give rise to problems in that the comparison of the addresses is too time consuming; the access time of a repaired memory may then deviate substantially from that of a correctly operating, non-repaired memory. When the memory is accommodated in a single chip, the surface area occupied thereby may be larger than could be expected on the basis of the added rows and/or columns in that the redundancy circuit is not very compatible with the architecture of the memory.
An important contribution to the elimination of these problems is made in European Patent Application No. 0 215 485 which corresponds to U.S. Pat. No. 4,748,597. In the memory described therein, no direct comparison is performed between a memory address presented and an address of a defective memory row or column which is programmed, for example by means of fuse elements. Said European Patent Application describes a memory which has a redundant storage space as described in the preamble and in which the redundancy address decoder comprises a logic gate circuit whose inputs receive the predecoded address bits via relevant fuse elements. The redundancy address decoder therein aims to minimize the number of fuse elements to be openened in the case of a defective row or column. However, this has resulted in a construction in which the gate depth of on the one hand the logic gate circuit in the redundancy address decoder and of the logic gate circuits in the main address decoder on the other hand differ substantially. For example, in FIG. 2 of said European Patent Application the redundancy address decoder comprises an 8-input gate circuit while the main address decoder comprises 2-input gate circuits, implying a comparatively large difference in gate depth. Consequently, the redundancy address decoder is too slow in comparison with the corresponding decoding channels in the main address decoder. This slow operation could lead to unacceptable results when a large memory is to be manufactured; due to the number of predecoded address bits which is much larger in that case, the gate depth of the redundancy address decoder will be greater accordingly.